## HORIZON: An Agentic Approach to Hardware Design Verification
NVIDIA Research has announced **HORIZON**, an advanced framework that automates hardware design by treating it as an iterative, version-controlled process. The system represents a significant step toward fully autonomous hardware development, using agentic workflows to evolve Register-Transfer Level (RTL) designs, testbenches, and verification artifacts.
HORIZON operates by treating each hardware design task as a **version-controlled repository**, rather than a single-shot generation exercise. The process begins with a **structured Markdown harness** that defines four key components: a design goal, domain-specific knowledge, an evaluator specification, and an acceptance predicate. A bootstrap agent then compiles this harness into a complete project pack and initiates an autonomous loop.
### The Autonomous Design Loop
Once initiated, HORIZON runs a continuous, hands-free loop. In each cycle:
1. The agent proposes changes to the current design.
2. The framework applies these changes to the working repository (a git worktree).
3. A comprehensive evaluator compiles, simulates, and checks the design.
4. An acceptance predicate determines whether the new version is committed.
The framework leverages standard `git` commands to manage its progression. Commits represent accepted design states, notes capture evaluation outcomes, and the full log serves as a replayable record of the design journey. HORIZON borrows terminology from semi-Markov decision processes to define “states” and “options” but does not train reinforcement learning policies. Instead, the backbone model remains fixed while the repository history acts as both memory and experience buffer.
### Benchmark Performance
Testing was conducted using a fixed GPT-5.3 backbone across multiple benchmark suites, including **ChipBench**, **RTLLM-2.0**, **Verilog-Eval-v2**, and the **CVDP** collection. The results were remarkable:
| Suite / Category | Iteration 0 Pass Rate | Convergent Pass Rate | Convergence Iterations |
|——————-|———————-|———————|————————|
| ChipBench (Mixed RTL) | 20.0% | 100.0% | 5 |
| RTLLM-2.0 (NL to RTL) | 78.0% | 100.0% | 2 |
| Verilog-Eval-v2 | 86.2% | 100.0% | 2 |
| CVDP CID 002 (RTL Completion) | 3.2% | 100.0% | 82 |
| CVDP CID 003 (NL to RTL) | 19.2% | 100.0% | 24 |
| CVDP CID 004 (RTL Modification) | 10.9% | 100.0% | 36 |
| CVDP CID 005 (Module Reuse) | 9.1% | 100.0% | 14 |
| CVDP CID 012 (Stimulus Gen) | 47.8% | 100.0% | 32 |
The **aggregate first-iteration pass rate** across all categories was **47.8%**, with many categories reaching 100% within just a few iterations. However, some tasks—particularly code completion (CID 002)—required hundreds of iterations due to long-horizon verification needs, highlighting where current models still face efficiency challenges.
### System Comparisons
HORIZON extends a lineage of self-evolving systems:
| System | Evolves | Domain | Evaluation |
|——–|———|——–|————|
| AlphaEvolve | Algorithmic kernels | Scientific | Automated evaluators |
| SATLUTION | SAT solvers | Formal verification | Correctness & runtime |
| ABCEvo | Logic synthesis | EDA | Correctness & QoR |
| **HORIZON** | **RTL + testbenches** | **Hardware design** | **Compile, simulate, coverage, assertions** |
All four systems share a core principle: candidate changes are accepted only when supported by executable evidence.
### Token Economics and Efficiency
The majority of computational cost is concentrated in the verification phase. The nine CVDP categories, representing 97.1% of total tokens, consumed **203.9M tokens** out of approximately **210M total**. The **CID 002** category alone accounted for **56M tokens** across 82 iterations. In contrast, the prompt cache significantly reduced billed tokens, with approximately **91% of inputs served from cache**, leaving only around **9% newly billed** for diffs and evaluator outputs.
According to the researchers, while final pass rates are strong, **token efficiency remains the primary area for future improvement**. The framework demonstrates that design quality can be driven by verifiable, iterative feedback—a model that could reshape electronic design automation.
**Original Article:** *NVIDIA Research introduced HORIZON, a hands-free agent framework for hardware design…* [MarkTechPost, July 4, 2026](https://www.marktechpost.com/2026/07/04/nvidia-horizon-a-hands-free-agent-that-evolves-git-worktrees-and-hits-100-rtl-benchmark-completion/)
